Subject: $root and "top level" instantiations
From: Gordon Vreugdenhil (gvreugde@synopsys.com)
Date: Mon Aug 12 2002 - 15:03:25 PDT
I would appreciate some feedback on the intent of $root
and "top level" instantiations as described in Sect 12.2
of the SystemVerilog 3.0 specification.
The relevant text in the LRM is in Section 12.2 (on pg 51):
"The order of elaboration shall be: First, look for explicit
instantiations in $root. If none, then look for implicit
instantiations (i.e. uninstantiated modules)..."
... snip ...
"A module can be explicitly instantiated in the $root top-level. All
uninstantiated modules become implicitly instantiated within the top
level, which is compatible with Verilog."
1) If you explicitly instantiate one or more modules in $root, do
uninstantiated modules get implicitly instantiated? The two
quotes seem to imply contradictory answers.
2) Do implicitly instantiated modules get instantiated in $root or
in some "top level" along with $root? Or does this depend on
whether $root has any explicit instantiations? What if $root
is non-empty (ie. has global data or type declarations) but
has no instantiations?
This seems to be an area in which some clarification might be
useful in the spec.
Gord.
-- ---------------------------------------------------------------------- Gord Vreugdenhil gvreugde@synopsys.com Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054 Synopsys Inc., Beaverton OR
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