Subject: Re: $root and "top level" instantiations
From: Peter Flake (flake@co-design.com)
Date: Thu Aug 15 2002 - 05:43:03 PDT
Hi Gordon,
At 03:03 PM 8/12/02 -0700, Gordon Vreugdenhil wrote:
>I would appreciate some feedback on the intent of $root
>and "top level" instantiations as described in Sect 12.2
>of the SystemVerilog 3.0 specification.
>
>The relevant text in the LRM is in Section 12.2 (on pg 51):
>
>"The order of elaboration shall be: First, look for explicit
>instantiations in $root. If none, then look for implicit
>instantiations (i.e. uninstantiated modules)..."
>
>... snip ...
>
>"A module can be explicitly instantiated in the $root top-level. All
>uninstantiated modules become implicitly instantiated within the top
>level, which is compatible with Verilog."
The qualification "If there is no explicit top level instantiation, then
all uninstantiated modules .... " was removed in draft 5.
>1) If you explicitly instantiate one or more modules in $root, do
> uninstantiated modules get implicitly instantiated? The two
> quotes seem to imply contradictory answers.
Not instantiated according to the original spec.
>2) Do implicitly instantiated modules get instantiated in $root or
> in some "top level" along with $root? Or does this depend on
> whether $root has any explicit instantiations? What if $root
> is non-empty (ie. has global data or type declarations) but
> has no instantiations?
If a module is implicitly instantiated, its hierarchical name given by %m
should not contain $root for Verilog compatibility.
Regards,
Peter.
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