Subject: static symmetry
From: Steven Sharp (sharp@cadence.com)
Date: Tue Oct 08 2002 - 14:06:37 PDT
Karen,
In writing up the argument on removing the keyword "static", I want to
fairly represent all of the issues. You said that one of the issues for
you was symmetry. Can you explain how this is an issue? Verilog-2001
doesn't include declarations of individual variables as being automatic,
so what would declarations of individual variables as being static be
symmetrical with?
Are you still holding on to the idea of declaring storage classes for each
variable as in C, instead of declaring tasks and functions to be reentrant
(or more properly, potentially reentrant if you don't mess them up with
incorrect references to static variables)? Or are you suggesting that users
be allowed to explicitly declare that a function or task is static, instead
of relying on that being the default?
Steven Sharp
sharp@cadence.com
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