Subject: RE: SystemVerilog 3.0 Is An Accellera Standard
From: Erich Marschner (erichm@cadence.com)
Date: Mon Nov 18 2002 - 08:15:47 PST
Vassilios,
Thanks for the clarification. Can you also address how and when conflicts between System Verilog 3.0 and IEEE 1364 Verilog will be addressed? If System Verilog 3.0 is stable at this point, does that mean that you do not expect it to change to be consistent with IEEE 1364 Verilog? If so, does that mean that you expect System Verilog to exist as a separate standard?
Regards,
Erich
-------------------------------------------
Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: erichm@cadence.com
Vmail: +1 410 872 4369 Email: erichm@comcast.net
| -----Original Message-----
| From: Vassilios.Gerousis@Infineon.Com
| [mailto:Vassilios.Gerousis@Infineon.Com]
| Sent: Monday, November 18, 2002 2:46 AM
| To: sv-bc@eda.org
| Subject: SystemVerilog 3.0 Is An Accellera Standard
|
|
| Dear SV-BC members,
| I want to clarify that SystemVerilog 3.0 is an
| Accellera Standard.
| We have offered to help clarify or enhance SystemVerilog. As language
| becomes a standard, users and EDA vendors must look at this
| as a stable
| standard ready for implementation. We also need to have a
| stable base to
| help in the development of additional components of
| SystemVerilog 3.1. We
| have provided an opportunity to correct mistakes or problems
| that were
| encountered during implementation. Harry Foster has
| implemented one of the
| assertion and found a mistake and this is being corrected,
| as an example.
| Intel is providing good feedback on the BNF.
| As we put the different components we may have to adjust certain
| things, but that will be kept at minimum. So I urge you that
| examine your
| work as clarification and enhancements to the existing
| capabilities. If the
| interface require additional improvement, then you need to
| build a proposal
| to do so.
|
| Best Regards
|
| Vassilios
|
| -------------------------------------------------------------
| ---------------
| --------------------------------------------------
| Dr. Vassilios Gerousis
| Chief Scientist
| Infineon Technologies
| DAT CS, MchB
| D-81541 Munich
| Germany
| BalanSt. 73
| Telephone: +49-89-234-21342
| Fax: +49-89-234-23650
| email: Vassilios.Gerousis@infineon.com
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