Subject: SystemVerilog 3.0 Is An Accellera Standard
From: Vassilios.Gerousis@Infineon.Com
Date: Sun Nov 17 2002 - 23:46:12 PST
Dear SV-BC members,
I want to clarify that SystemVerilog 3.0 is an Accellera Standard.
We have offered to help clarify or enhance SystemVerilog. As language
becomes a standard, users and EDA vendors must look at this as a stable
standard ready for implementation. We also need to have a stable base to
help in the development of additional components of SystemVerilog 3.1. We
have provided an opportunity to correct mistakes or problems that were
encountered during implementation. Harry Foster has implemented one of the
assertion and found a mistake and this is being corrected, as an example.
Intel is providing good feedback on the BNF.
As we put the different components we may have to adjust certain
things, but that will be kept at minimum. So I urge you that examine your
work as clarification and enhancements to the existing capabilities. If the
interface require additional improvement, then you need to build a proposal
to do so.
Best Regards
Vassilios
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Dr. Vassilios Gerousis
Chief Scientist
Infineon Technologies
DAT CS, MchB
D-81541 Munich
Germany
BalanSt. 73
Telephone: +49-89-234-21342
Fax: +49-89-234-23650
email: Vassilios.Gerousis@infineon.com
Site Map:
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
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