Subject: Re: Two minor suggestions for enriching the system verilog syntax
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Dec 04 2002 - 08:41:39 PST
Hi Eric;
Speaking of your suggestions in the reverse order;
For implicit partial matches, there is a further capabilities in this area that
HP has written up (and other companies also have.)
It involves allowing the port specification to be a regular expression.
So in your example,
>For example
> alu alu1 ( .alu_out(alu_out1), .*in(*in1), .* );
> alu alu2 ( .alu_out(alu_out2), .*in(*in2), .* );
>
>This would imply the .ain(ain1) and .bin(bin1) connections
>for alu1 and the .ain(ain2) and .bin(bin2) connections for alu2.
You could make connections like:
.(.*)in (${1}in1)
Which would connect ain to ain1, bin to bin1, etc.
With capabilities like this you can also do things like
.alu(.*) (alu0$1)
.(.*?)mac(.*) ($1_mac2_$2)
This then allows users to define matching ports and restructure the connecting net name.
However this functionality is sufficiently advanced. I wonder how hard it will be to
debug port connections when one can't see the resulting connection set as you can now
do with your preprocessor.
I do like your suggestion to use both .name and .* together. The only reason I heard for
not allowing both sounded like a methodology issue which people ignore as justification
for limitations.
On the topic of making the default library list the entire set of libraries instead
of the library of the top module.
It would be a more reasonable default. Model Technologies has a usage model like this,
but they require a specified list of libraries. Can anyone comment on the usage model
of NC wrt the issue of specifying libraries?
Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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