Subject: Cadence Technical Analysis of System Verilog
From: Jay Lawrence (lawrence@cadence.com)
Date: Wed Dec 04 2002 - 18:10:38 PST
SV-Committee members:
Attached please find the presentation given in the SV meeting today.
I've removed the "Cadence Confidential" footers. Vassilios, if you are
posting the presentation anywhere please use the attached copy not the
one on the floppy you have from today. The content is unchanged except
for the footers.
Thanks for all your time and energy today. Many of you found me after
the meeting with both positive and negative comments on Cadence's
analysis; I welcome comments back to the reflector or sent directly to
me at lawrence@cadence.com. I will also be at the seminar tomorrow at
the Marriott and available if you want to have any further face-to-face
discussion while I'm still on the west coast.
Sincerely,
Jay Lawrence
Cadence Design Systems, Inc.
Architect - Logic Verification
978 262-6294
lawrence@cadence.com
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