Subject: Re: Cadence Technical Analysis of System Verilog
From: Jayant Nagda (Jayant.Nagda@synopsys.com)
Date: Fri Dec 20 2002 - 14:56:21 PST
I am forwarding this on behalf of Phil Moorby since his latest email
is not on the reflector.
Jayant Nagda
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Subject: Cover email text
Date: Fri, 20 Dec 2002 17:48:50 -0500
From: "Phil Moorby" <moorby@synopsys.COM>
To: TCC-Chair Vassillios Gerousis
CC: SystemVerilog committee members.
Cadence presented a technical response to SystemVerilog on December 4th
in
San Jose, CA (attached as pdf file).
We, as key contributors to the SystemVerilog language, have provided as
attached pdf file a technical
clarification response to the questions and issues raised.
SystemVerilog is the work of many excellent contributors, and these
clarifications we hope will help
participating members understand that SystemVerilog is building a solid
extension to the Verilog standard.
Users will benefit tremendously with the advancement, completeness and
standardization of this language.
We hope that Cadence will join us constructively in this effort.
Phil Moorby, Synopsys Scientist.
December, 2002
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