Passed simple changes

Subject: Passed simple changes
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Fri Dec 20 2002 - 13:14:41 PST

• Next message: Jayant Nagda: "Re: Cadence Technical Analysis of System Verilog"
• Previous message: Karen Pieper: "SV-BC Edits as of 12/20/02"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Hi, all,

        I've attached the easy issues that passed at 12 noon today. They have
been forwarded to Stu
for inclusion in the next draft of the standard.

Enjoy!

K

• text/html attachment: Easy_Issues_02_12_13.htm

• Next message: Jayant Nagda: "Re: Cadence Technical Analysis of System Verilog"
• Previous message: Karen Pieper: "SV-BC Edits as of 12/20/02"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

This archive was generated by hypermail 2b28 : Fri Dec 20 2002 - 13:15:07 PST