Subject: SV-BC2 - timescale vs timeunit
From: Francoise Martinolle (fm@cadence.com)
Date: Mon Jan 13 2003 - 07:37:51 PST
I reviewed the timescalre versus time unit proposal.
Here are my comments and issues.
Issue 1: The spec does not say (or is not clear enough) if you can have
both a 'timescale and a
timeunit and time precision declaration applied to a module or interface
declaration.
I am assuming that the sentence :
"There can be only one time unit and one time precision for any module or
interface definition or in $root."
is meant for that purpose, but it may need to be reworded to say one
timescale compiler directive
or time unit declaration if the intent was to say that you cannot have both...
Example1:
is it legal to write:
'timescale 10ns/1ns; -> compiler directive
....
....
module top
time unit 1 ns; -> declaration
time precision 1 ns; -> match the compiler directive
endmodule.
Can you have both directive and declarations which match?
Example2
is it legal to write:
'timescale 10ns/1ns;
....
....
module top
time unit 10 ns;
time precision 1 ns; -> match the compiler directive
endmodule.
Having both a timeunit/precision declaration and compiler directives can
happen very often while
bringing Verilog protected modules or trying to do modular design, I think
this should be
allowed.
Declarations and compiler directives are very different semantically.
However in order to
express exactly the behaviour of a time unit or precision declaration we
can perhaps define it by specifying the equivalence between local
declarations in a module and a
'timescale preceding the module and the timescale reset at the end of the
module?
Issue 2:
Why allowing multiple declarations of time unit and precision in the same
scope?
Is it in the case where the declarations appear both in the module and an
interface that
the module would be using?
interface a (input bit clk);
time unit 10 ns;
//no time precision
logic req, gnt;
endinterface
'timescale 100ns/1ns; -> compiler directive
....
....
module memmod ( interface a)
time unit 1 ns; -> declaration
time precision 1 ns; -> match the earlier compiler directive
always @(posedge a.clk)
#1.05 a.gnt <= a.req; -> what is the resulting delay used for the
assignment?
endmodule.
Francoise
'
> * SV-BC2 - timescale vs. timeunit
> * This is a write-up of the behavior agreed upon at the 11/15 F2F
> * http://www.eda.org/sv-bc/hm/0224.html - posted 12/6/02 by Dave Rich
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