Subject: Re: SV-BC2 - timescale vs timeunit
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Jan 13 2003 - 09:06:50 PST
Françoise,
I should have formatted my proposal to distinguish between the
terminology "time unit" and the keyword "timeunit", which should be in
bold courier font. If have attached a PDF version (with a few grammar
corrections suggested by Word).
See other comments below.
Francoise Martinolle wrote:
> I reviewed the timescale versus time unit proposal.
>
> Here are my comments and issues.
>
> Issue 1: The spec does not say (or is not clear enough) if you can
> have both a 'timescale and a
> timeunit and time precision declaration applied to a module or
> interface declaration.
The rules of precedence should cover this. You can have both, but the
timeunit will override.
>
>
> I am assuming that the sentence :
> "There can be only one time unit and one time precision for any module
> or interface definition or in $root."
> is meant for that purpose, but it may need to be reworded to say one
> timescale compiler directive
> or time unit declaration if the intent was to say that you cannot have
> both...
>
> Example1:
> is it legal to write:
yes
>
> 'timescale 10ns/1ns; -> compiler directive
> ....
> ....
> module top
> time unit 1 ns; -> declaration
> time precision 1 ns; -> match the compiler directive
Once there is a timeunit/timeprecision declaration, the compiler
directives no longer applies
>
>
> endmodule.
>
> Can you have both directive and declarations which match?
Doesn't matter. declaration overrides directive.
>
>
> Example2
> is it legal to write:
> 'timescale 10ns/1ns;
> ....
> ....
> module top
> time unit 10 ns;
> time precision 1 ns; -> match the compiler directive
>
> endmodule.
>
>
> Having both a timeunit/precision declaration and compiler directives
> can happen very often while
> bringing Verilog protected modules or trying to do modular design, I
> think this should be
> allowed.
> Declarations and compiler directives are very different semantically.
> However in order to
> express exactly the behaviour of a time unit or precision declaration we
> can perhaps define it by specifying the equivalence between local
> declarations in a module and a
> 'timescale preceding the module and the timescale reset at the end of
> the module?
>
> Issue 2:
> Why allowing multiple declarations of time unit and precision in the
> same scope?
This was primarily meant for $root and applied to other scopes for
completeness.
>
> Is it in the case where the declarations appear both in the module and
> an interface that
> the module would be using?
>
>
> interface a (input bit clk);
> time unit 10 ns;
> //no time precision
> logic req, gnt;
> endinterface
>
> 'timescale 100ns/1ns; -> compiler directive
This should generate a compiler error because you are now specifying a
time precision when previous code had none specified. This is the same
as having the first `timescale directive appear after a module with no
`timescale directive.
>
> ....
> ....
> module memmod ( interface a)
> time unit 1 ns; -> declaration
> time precision 1 ns; -> match the earlier compiler directive
>
> always @(posedge a.clk)
> #1.05 a.gnt <= a.req; -> what is the resulting delay used for the
> assignment?
>
> endmodule.
>
> Francoise
> '
>
>> 1. * SV-BC2 - timescale vs. timeunit
>> 2. * This is a write-up of the behavior agreed upon at the 11/15 F2F
>> 3. _ http://www.eda.org/sv-bc/hm/0224.html
>> _ - posted 12/6/02 by Dave Rich
>>
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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