Subject: RE: several proposal submitted for email voting
From: Jay Lawrence (lawrence@cadence.com)
Date: Mon Jan 13 2003 - 08:40:19 PST
Yes, but abstaining is very different than voting yes.
If for instance I went on vacation and came back having taken no action on a vote and found I was signed up as a "for" vote I'ld be pretty upset.
Jay
===================================
Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Dave Rich [mailto:David.Rich@synopsys.com]
> Sent: Monday, January 13, 2003 11:05 AM
> To: Francoise Martinolle
> Cc: Srouji, Johny; sv-bc@eda.org
> Subject: Re: several proposal submitted for email voting
>
>
> Françoise,
>
> In this type of voting, any response will just postpone the vote to a
> later vote, be it e-mail or an actual meeting, so no response is the
> same as no objection to letting it pass.
>
> Dave
>
>
> Francoise Martinolle wrote:
>
> > Johny,
> >
> > typically in other committees, anyone not voting is assumed
> to abstain.
> > It seems to me more logical than assuming they approved. Some people
> > may not vote because they don't care, forgot or were not available.
> >
> > What other people think?
> >
> > Francoise
> > '
> >
> > At 04:39 PM 1/12/2003 +0200, Srouji, Johny wrote:
> >
> >> Hi All,<?xml:namespace prefix = o ns =
> >> "urn:schemas-microsoft-com:office:office" />
> >>
> >>
> >>
> >> Attached are several proposals that have a second, and
> because they
> >> were previously discussed, we are likely able to pass them without
> >> further discussions. Therefore, I move that we vote on
> these topics
> >> through mail.
> >>
> >>
> >>
> >> Let me know if you have an issue w/ any of these
> proposals, or send
> >> your vote/clarification/discussions. Anyone not voting will be
> >> assumed to approve the changes. Voting will close by next Monday,
> >> 01//20/2003 at 11:00 AM (right after our tele-call). If
> there is no
> >> discussion of any of these items by this date, then
> proposal will pass.
> >>
> >>
> >>
> >> Following is the list of proposals:
> >>
> >>
> >>
> >> 1. * SV-BC2 - timescale vs. timeunit
> >> 2. * This is a write-up of the behavior agreed upon at
> the 11/15 F2F
> >> 3. _ http://www.eda.org/sv-bc/hm/0224.html
> >> 4. _ - posted 12/6/02 by Dave Rich* SV-BC44-3 self determination
> >> of assignment as expression
> >> 5. * _ http://www.eda.org/sv-bc/hm/0271.html
> >> 6. _ - posted 12/26/02 by Dave Rich* SV-BC44-9 behavior
> of disable
> >> 7. *_ http://www.eda.org/sv-bc/hm/0272.html
> >> 8. _ - posted 12/26/02 by Dave Rich* SV-BC44-15 removal
> of "changed"
> >> 9. * _ http://www.eda.org/sv-bc/hm/0273.html
> >> 10. _ - posted 12/26/02 by Dave Rich* Clarification of operations
> >> allowed on unpacked arrays
> >> 11. * SystemVerilog allows certain operations on
> aggregate unpacked
> >> arrays. From LRM section 4.2, it allows read and writes as a
> >> whole or slice of an unpacked array, but not as part of an
> >> integer expression. From this wording, it is unclear as to
> >> whether or not a comparison of two unpacked arrays would be
> >> allowed.
> >> 12. Karen proposed that we append a bullet to the first list of
> >> bullets that reads:
> >> 13. -- Equality operations the array or slice of the array,
> >> e.g. A==B, A[i:j] != B[i:j]
> >> 14. Also a small correction to the preceding paragraph
> >> 15. Replace:
> >> 16. The examples provided with these rules assume that A
> and B are
> >> arrays.
> >> 17. With:
> >> 18. The examples provided with these rules assume that A
> and B are
> >> arrays of the same shape and type.
> >>
> >> Regards,
> >>
> >> --- Johny.
> >>
> >
>
> --
> --
> Dave Rich
> Principal Engineer, CAE, VTG
> Tel: 650-584-4026
> Cell: 510-589-2625
> DaveR@Synopsys.com
>
>
>
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