Subject: Re: packed arrays other than bit,logic,reg and wire
From: Dave Rich (David.Rich@synopsys.com)
Date: Thu Jan 16 2003 - 15:19:01 PST
Steven,
The problem has to do with the "de-facto" Verilog standard that
currently allows people to declare
integer [31:0] a;
and the range is ignored. If we allow packed arrays of integers, then
the declaration becomes ambigious.
Even without this problem, the syntax for a packed array of 32 integers
would look misleading.
Also, hardware engineers tend not to think about integers as having a
fixed size.
Dave
Steven Sharp wrote:
>I see no reason why you shouldn't be able to create a packed array of
>integers. An integer is effectively just a packed array of logic, and
>you can create packed arrays of packed arrays already.
>
>Steven Sharp
>sharp@cadence.com
>
>
>
>
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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