Subject: Re: packed arrays other than bit,logic,reg and wire
From: Steven Sharp (sharp@cadence.com)
Date: Thu Jan 16 2003 - 16:01:04 PST
>The problem has to do with the "de-facto" Verilog standard that
>currently allows people to declare
>
>integer [31:0] a;
>
>and the range is ignored. If we allow packed arrays of integers, then
>the declaration becomes ambigious.
I had forgotten about that, and I agree that it is a concern. However,
it is fairly obscure and is not supported by the written standard.
NC-Verilog produces a warning for it. Verilog-XL produces a warning
for it that explicitly says that it will be disallowed in future releases.
It may be reasonable to deprecate it in Verilog (though it is a little
awkward to officially deprecate a "feature" that was never officially part
of the language).
Packed arrays of integers aren't necessarily an important thing. However,
I believe that the int type should be defined as a typedef instead of
being a new keyword. That typedef would be as a signed packed array of bit.
This would allow int to be used in packed arrays. That would make it odd
if integers were not allowed in packed arrays.
>Also, hardware engineers tend not to think about integers as having a
>fixed size.
And officially they don't. The standard only requires that they be at
least 32 bits. But that means that either int needs to become the same
non-fixed size, or integers and ints are not consistent with each other
again. Is anyone aware of a simulator where integers are not exactly
32 bits?
Steven Sharp
sharp@cadence.com
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