Subject: Re: packed arrays other than bit,logic,reg and wire
From: Dave Rich (David.Rich@synopsys.com)
Date: Thu Jan 16 2003 - 16:51:33 PST
Steven Sharp wrote:
>>The problem has to do with the "de-facto" Verilog standard that
>>currently allows people to declare
>>
>>integer [31:0] a;
>>
>>and the range is ignored. If we allow packed arrays of integers, then
>>the declaration becomes ambiguous.
>>
>>
>
>I had forgotten about that, and I agree that it is a concern. However,
>it is fairly obscure and is not supported by the written standard.
>NC-Verilog produces a warning for it. Verilog-XL produces a warning
>for it that explicitly says that it will be disallowed in future releases.
>It may be reasonable to deprecate it in Verilog (though it is a little
>awkward to officially deprecate a "feature" that was never officially part
>of the language).
>
The fact that so many simulators support it will make it hard to remove.
It is not as obscure as you might think. Try to develop a Verilog
simulator today without supporting it!
Once SystemVerilog is introduced, it will be very difficult to track down.
>>Also, hardware engineers tend not to think about integers as having a
>>fixed size.
>>
>>
>
>And officially they don't. The standard only requires that they be at
>least 32 bits. But that means that either int needs to become the same
>non-fixed size, or integers and ints are not consistent with each other
>again. Is anyone aware of a simulator where integers are not exactly
>32 bits?
>
Packed objects should be thought as concatenations of other objects, and
having a non-fixed size in a concat is not legal. Things get worse with
packed unions. If you allow non-fixed sided objects in packed unions,
descriptions that legally compile in some implementations will not
legally compile in others.
>
>Steven Sharp
>sharp@cadence.com
>
>
-- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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