Subject: [sv-bc] Removal of the SystemVerilog logic data type
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Jan 23 2003 - 09:06:12 PST
Hi, All -
Is somebody going to summarize the changes to data types and permissible
assignments from yesterday's meeting? I would like to look at the passed
straw-votes with an eye towards making one more stab at slight
modifications to satisfy the desires of actual users. I noted that in
yesterday's meeting, there were only three users, myself, Kev (who
represents AMS very well) and Matt, and since Matt already had what he
wanted, he was somewhat neutral on the proposals. Everyone else in the
meeting was a tool representative and I think the proposals passed fell
short of user enhancement expectations and representation.
I would like to understand what we passed and then open a debate among
users to see if we are giving them what they want. I think we are close but
not close enough.
I really think most Verilog users want the VHDL equivalent of the std_logic
type, which can be assigned from either one or more processes with
last-assignment-wins behavior or one or more concurrent signal assignments
with resolved behavior, except in true Verilog style, users (myself
included) do not want to have to make the equivalent declarations.
Some of the highlights (lowlights?) from yesterdays meeting (according to
my understanding?)
- logic is not and never was a universal data type (somebody needs to tell
Stu to change his presentation)
- as a matter of fact, logic was removed from SystemVerilog altogether
yesterday (Stu needs to change his presentation)
- there will be a new varport (was this the name?) type for shared
variable-like ports to replace the previous shared-port behavior of logic
- regs are now (the/a??) default type and we can now make one or more
procedural assignments or one continuous assignment to a reg variable
- scalar regs do not have to be declared
- multiple continuous assignments or multiple driver-assignments within a
module must still be done to a net type
BTW - does this mean that almost all interface logic declarations will now
have to be reg declarations because one side of the interface is frequently
a procedural assignment and the other side is an input? (looks strange to me)
I know that Jay is talking about doing away with interfaces by replacing
them with either just modules or enhanced modules(?)
A better summary of this discussion and corrections to my understanding
above would be appreciated.
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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