Subject: Re: [sv-bc] Removal of the SystemVerilog logic data type
From: Gordon Vreugdenhil (gvreugde@synopsys.com)
Date: Thu Jan 23 2003 - 09:31:50 PST
Cliff, see my notes below -- this should be clarified by the
official minutes as well.
"Clifford E. Cummings" wrote:
>
> Hi, All -
>
[...]
> Some of the highlights (lowlights?) from yesterdays meeting (according to
> my understanding?)
> - logic is not and never was a universal data type (somebody needs to tell
> Stu to change his presentation)
Correct.
> - as a matter of fact, logic was removed from SystemVerilog altogether
> yesterday (Stu needs to change his presentation)
Remember -- this was only a straw poll. Part of the objective of
doing the straw poll was to draw out any final concerns from the
group. After the straw poll on removing logic, there was subsequent
discussion that made a very good case for not removing it even
though it is now functionally redundant. I don't think that the
final proposal for the official vote will suggest removing it.
> - there will be a new varport (was this the name?) type for shared
> variable-like ports to replace the previous shared-port behavior of logic
"var" is going to be a port mode in the same was as "input", etc.
> - regs are now (the/a??) default type and we can now make one or more
> procedural assignments or one continuous assignment to a reg variable
reg is not the default type. You will be permitted to make a
single continuous assign to a reg assuming that the declaration
satisfies the constraints discussed (can't be a shared variable, etc).
> - scalar regs do not have to be declared
Discussed but not approved.
> - multiple continuous assignments or multiple driver-assignments within a
> module must still be done to a net type
Yes.
Gord.
-- ---------------------------------------------------------------------- Gord Vreugdenhil gvreugde@synopsys.com Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054 Synopsys Inc., Beaverton OR
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