Subject: Re: [sv-bc] Proposal for extern modules
From: Steven Sharp (sharp@cadence.com)
Date: Thu Feb 27 2003 - 14:58:52 PST
>The question is: do you want to support separate compilation?
It doesn't matter whether I want to support it or not. The Verilog
language contains constructs that prevent it. Extern modules would
only deal with the .* port issue. That still leaves hierarchical
references and parameter value propagation.
In a particular tool-specific application, accepting a limited subset
of the language, it may be possible to do a kind of separate compilation.
But for a tool that accepts the standard Verilog language, it is not
possible. Changing the standard Verilog language in this way does not
make it possible.
For the tool-specific application, dummy modules with "extern" attributes
should work fine. Attributes were added to the standard to support these
kinds of tool-specific mechanisms. They are an appropriate mechanism here.
Steven Sharp
sharp@cadence.com
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