Subject: [sv-bc] 7.3 -- Proposal
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Sat Mar 01 2003 - 06:48:45 PST
Proposal
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In section 7.3, after the paragraph that begins "SystemVerilog also
includes ...", ADD the following paragraph --
It shall be illegal to include an assignment, increment, or
decrement in an event expression, in an expression within a
procedural continuous assignment, or in an expression that
is not within a procedural statement.
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