[sv-bc] SV-BC79 -- Proposal


Subject: [sv-bc] SV-BC79 -- Proposal
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Sun Mar 02 2003 - 10:08:03 PST


Proposal
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In 23.1, REPLACE --

   SystemVerilog enhances the capabilities of the
   `define compiler directive to support strings
   as macro arguments.

WITH --

   SystemVerilog enhances the capabilities of the
   `define compiler directive to support the
   construction of string literals and identifiers
   and enhances the `include directive to accept
   a filename constructed with a macro.

---

In 23.2, REPLACE --

In SystemVerilog

with

In Verilog

---

and REPLACE --

The macro text can also include an isolated quote, which must be preceded by a back tic, `". This allows macro arguments to be included in strings. If the strings are to contain \", the macro text should be written `\`". Otherwise, the backslash will be treated as the start of an escaped identifier.

WITH

In SystemVerilog, the macro text can also include `", and `\`" and ``. An `" overrides the usual lexical meaning of " and indicates that the expansion should include an actual quotation mark. This allows string literals to be constructed from macro arguments. A `\`" indicates that the expansion should include the escape sequence \", e.g.

`define msg(x,y) `"x: `\`"y`\`"`"

This expands:

$display(`msg(left side,right side));

to:

$display("left side: \"right side\""); ---

and REPLACE

The macro text can also include a double back tick, ``, to allow identifiers to be constructed from arguments, e.g.

WITH

A `` delimits lexical tokens without introducing whitespace, allowing identifiers to be constructed from arguments, e.g.

---

and REPLACE

foo(bar)

WITH

`foo(bar)

---

and DELETE

Note that there must be no space before the parenthesis. Otherwise it is treated as macro text.

---

and REPLACE

`define f1 "/home/foo/myfile" `include `f1

WITH

`define home(filename) `"/home/foo/filename`" `include `home(myfile)

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