Subject: Re: [sv-bc] Proposal for SV-BC75 declarations in unnamed blocks
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Mar 03 2003 - 11:26:13 PST
Francoise Martinolle wrote:
> At 07:01 AM 3/3/2003 -0800, Dave Rich wrote:
>
>> In section 5.5 Scope and lifetime, REPLACE the paragraph"
>>
>> "Note that in SystemVerilog, data can be declared in unnamed blocks
>> as well as in named blocks, but in the
>> unnamed blocks a hierarchical name cannot be used to access it."
>>
>> WITH
>> "Note that in SystemVerilog, data can be declared in unnamed blocks
>> as well as in named blocks. This data is visible to the unnamed block
>> and any nested blocks below it. Hierarchical references cannot be
>> used to access this data by name.
>
>
> Even relative hierarchical references within the nested blocks are
> forbidden?
>
Can you show by example what code you have a question with? I did not
think 'relative' hierarchical references existed within a procedural block.
> Some tools may automatically generate scope names for data in these
> unnamed blocks, however, these generated scope names shall not be
> visible to the scopes below it."
This archive was generated by hypermail 2b28 : Mon Mar 03 2003 - 11:27:01 PST