Subject: Re: [sv-bc] Proposal for SV-BC75 declarations in unnamed blocks
From: Francoise Martinolle (fm@cadence.com)
Date: Mon Mar 03 2003 - 09:01:49 PST
At 07:01 AM 3/3/2003 -0800, Dave Rich wrote:
>In section 5.5 Scope and lifetime, REPLACE the paragraph"
>
>"Note that in SystemVerilog, data can be declared in unnamed blocks as
>well as in named blocks, but in the
>unnamed blocks a hierarchical name cannot be used to access it."
>
>WITH
>"Note that in SystemVerilog, data can be declared in unnamed blocks as
>well as in named blocks. This data is visible to the unnamed block and any
>nested blocks below it. Hierarchical references cannot be used to access
>this data by name.
Even relative hierarchical references within the nested blocks are forbidden?
>Some tools may automatically generate scope names for data in these
>unnamed blocks, however, these generated scope names shall not be visible
>to the scopes below it."
>
>--
>--
>Dave Rich
>Principal Engineer, CAE, VTG
>Tel: 650-584-4026
>Cell: 510-589-2625
>DaveR@Synopsys.com
>
>
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