Subject: [sv-bc] RE: [sv-ec] Assignments in event expressions
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Mon Apr 14 2003 - 19:15:26 PDT
The sentence in section 7.3 was added by the BC on 3/3/3 for SV-BC85
http://www.eda.org/sv-bc/hm/0561.html
http://www.eda.org/sv-bc/hm/0572.html
-- Brad
-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org]On Behalf Of Jay
Lawrence
Sent: Monday, April 14, 2003 6:56 PM
To: sv-bc@eda.org; sv-ec@eda.org
Subject: [sv-ec] Assignments in event expressions
David Smith, Dave Rich, and Johny Srouji,
While working on other issues surrounding SystemVerilog this evening I
came across an obvious conflict in the Draft 4 LRM. In section 7.3 it
says: "It shall be illegal to include an assignment expression in an
event control". Section 8.11 is entitled "Assignment expressions within
event controls" and explains how they will be handled.
Can we possibly just delete section 8.11 and leave these as illegal? It
appears to me from the change bars and editing that the sv-ec added
section 7.3 to eliminate a nasty situation and that 8.11 existed in the
3.0 standard.
Jay
===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
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