Subject: Re: [sv-bc] Process and schedule for final LRM vote
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Thu Apr 24 2003 - 16:16:14 PDT
Johny,
The IEEE 1364 members on the SV-BC are Stefen Boyd and Cliff Cummings. The
official IEEE 1364 member vote (with 100% consensus) is:
>_X_yes Approve sending the LRM (the work performed by SV-BC) to the
>board for their approval.
We would like to register a comment along with our vote: The IEEE 1364
members request that immediately after acceptance of SystemVerilog 3.1
standard by the Accellera board, Accellera begin the processes of donating
all or portions of the SystemVerilog 3.1 LRM to the IEEE 1364 Verilog
Standard Group for consideration to be included in the currently open PAR
to update the IEEE 1364 Verilog standard.
Stu Sutherland
At 12:34 AM 4/23/2003, Srouji, Johny wrote:
>Hi All,
>
>
>
>This is a reminder that I am expecting your votes by Tomorrow (Thu) 5:00
>pm PDT.
>
>I would appreciate that ALL members (including non eligible) vote, as your
>opinions will be tracked and it is important to hear your voice.
>
>
>
>For the representatives assigned below, please fill in the following line:
>
>
>
>__ YES __ NO Approve sending the LRM (the work performed by SV-BC) to
>the board for their approval.
>
>
>
>Thank you all for excellent work done!
>
>
>
>--- Johny.
>
>
>
>
>
>-----Original Message-----
>From: Srouji, Johny
>Sent: Monday, April 21, 2003 9:02 PM
>To: sv-bc@eda.org
>Cc: Srouji, Johny; 'Karen'; 'Vassilios.Gerousis@infineon.com'
>Subject: [SV-BC] Process and schedule for final LRM vote
>Importance: High
>
>
>
>Hi All,
>
>
>
>Following the TCC meeting last Friday and David Smith note capturing the
>voting process and schedule, I suggest that we follow a similar process
>for our committee, as outlined below. I have also made some suggestions.
>Please let me know ASAP if you have any comments or issues w/ this process.
>
>
>
>· We shall have the voting by EMAIL. If someone strongly feels we
>should have a meeting for this, send me a note.
>
>· Voting must complete by 24 April (Thursday) at 5:00 pm (pacific).
>
>· Based on the attendance rule of 3/4 last meetings - here is a
>list of eligible voting members for SV-BC:
>Johny Srouji (Intel),
>Karen Pieper (Synopsys),
>Gord Vreugdenhil (Synopsys),
>Brad Pierce (Synopsys),
>Francoise Martinolle (Cadence),
>Dan Jacobi (Intel),
>David Rich (Synopsys),
>Matt Maidment (Intel),
>
>Kevin Cameron (NSC) - OK attendance wise, but NSC is not an eligible member
>· All participants will vote by company (even non-eligible
>companies due to attendance or not being Accellera members). This is
>desired to make sure that all participant companies have a voice.
>non-eligible company votes will not be counted but they will be tracked.
>
>· I suggest that each of the voting companies choose a
>representative to submit their vote. Here is my suggestion for the
>eligible voting companies:
>Cadence: Francoise Martinolle
>Synopsis: David Rich
>Intel: Matt Maidment
>As for the non eligible companies:
>NSC: Kevin Cameron
>Sunburst Design: Cliff Cummings
>Model Technology: Dennis Brophy
>LCDM Engineering: Don Mills
>Verisity: Mike McNamara
>Boyd Technology: Stefen Boyd
>HMC: Heath Chambers
>Fintronic: Alec F. Stanculescu
>· Please send your vote directly to me
>(<mailto:johny.srouji@intel.com>johny.srouji@intel.com) and to Karen
>Pieper (<mailto:Karen.Pieper@synopsys.com>Karen.Pieper@synopsys.com)
>
>· The vote will be approved if 2/3s of the eligible companies vote
>and approve.
>
>· Each committee votes only on the work they have done (sections
>of the LRM or content to sections) as a single vote that indicates the
>committees work is to be sent to the board for acceptance.
>
>· The votes will be tallied on Friday.
>
>Thanks,
>
>
>
>--- Johny.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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