[sv-bc] Fwd: BOUNCE sv-bc@eda.org: Non-member submission from [Raghuraman R <raghu@ti.com>]


Subject: [sv-bc] Fwd: BOUNCE sv-bc@eda.org: Non-member submission from [Raghuraman R ]
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Fri Apr 25 2003 - 08:47:15 PDT


>Date: Thu, 24 Apr 2003 20:47:39 -0700 (PDT)
>From: owner-sv-bc@eda.org
>To: owner-sv-bc@eda.org
>Subject: BOUNCE sv-bc@eda.org: Non-member submission from [Raghuraman R
><raghu@ti.com>]
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> >From owner-sv-bc Thu Apr 24 20:46:56 2003
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>Message-ID: <3EA8AFA3.7050505@ti.com>
>Date: Fri, 25 Apr 2003 09:16:43 +0530
>From: Raghuraman R <raghu@ti.com>
>Organization: Texas Instruments (India) Ltd.
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>To: Michael.Burns@motorola.com
>CC: david.smith@synopsys.com, sv-bc@server.eda.org, sv-ec@server.eda.org
>Subject: Re: FW: [sv-ec] Section 19 of Draft - Interfaces
>References: <000701c30a7d$4b945d30$3c29040a@Ramirez>
><200304241922.h3OJM8A12356@nacho.sps.mot.com>
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>
>Thanks for the response.
>
>If I want to instantiate not the third-least-significant bit, but say
>the second-least-significant bit, does the current standard allow
>
>dummy dummy_inst(.A({,wir1,}), .B(wir2), .Y(wir3));
>
>and one more point is that it mandates the knowledge of bus width. If
>one does not want the instantiation to know the bus width, then the
>above syntax wont be good enough.
>
>My point is that the syntaxt
>
>dummy dummy_inst(.A[4](wir1), .B(wir2), .Y(wir3));
>
>will work as long as there is a legal A[4].
>
>It could be A[0:4] or A[4:0] or A[4:7] or A[7:4].
>
>There could be an extension to the the above syntax as well in the form of
>
>dummy dummy_inst(.A[4:7]({wir1,wir2,wir3,wir4}),.B(wir5),.C(wir6));
>
>Thanks.
>
>Michael Burns wrote:
> > The problem I see with your proposed syntax is that, without looking
> > at the port declaration (i.e., without knowing how big the port is or
> > how the bits are numbered), you have no idea if you're connecting to
> > the MSB of the port, the LSB, some bit in the middle, or even an
> > illegal bit (for example, the port declaration could specify a range
> > of [7:4]). Right now, I think you can also do this:
> >
> > wire wir1,wir2,wir3;
> > dummy dummy_inst(.A({wir1,,}), .B(wir2), .Y(wir3));
> >
> > to connect to the third-least-significant bit, though you may have to
> > endure compiler warnings about mismatched connection sizes.
> >
> > Mike Burns
> >
> >
> >>A question sent to the EC reflector that I think BC may also want to
> answer.
> >>
> >>Regards
> >>David
> >>
> >>David W. Smith
> >>Synopsys Scientist
> >>
> >>Synopsys, Inc.
> >>Synopsys Technology Park
> >>2025 NW Cornelius Pass Road
> >>Hillsboro, OR 97124
> >>
> >>Voice: 503.547.6467
> >>Main: 503.547.6000
> >>FAX: 503.547.6906
> >>Email: david.smith@synopsys.com
> >>http://www.synopsys.com
> >>
> >>
> >>
> >>-----Original Message-----
> >>From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
> >>Raghuraman R
> >>Sent: Wednesday, April 23, 2003 11:11 PM
> >>To: sv-ec@eda.org
> >>Subject: [sv-ec] Section 19 of Draft - Interfaces
> >>
> >>
> >>Hi,
> >>
> >>In the module instantiation section, I have this issue.
> >>
> >>If we are having a module having a port say
> >>
> >>module dummy (A, B, Y)
> >>input [0:3] A;
> >>input B;
> >>output Y;
> >>endmodule
> >>
> >>and we want to instantiate the module dummy with only bit of the port A
> >>instantiated, we need something like this
> >>
> >>wire wir1,wir2,wir3;
> >>dummy dummy_inst(.A[1](wir1), .B(wir2), .Y(wir3));
> >>
> >>Currently the way to do it is
> >>
> >>dummy dummy_inst(.A{,wir1,,,},.B(wir2), .Y(wir3));
> >>But for this, we have to know the size of the port, but I think with the
> >>existing information, one should to be able to instantiate and proceed.
> >>
> >>Thanks.
> >>
> >>Thanks.
> >>--
> >>Regds,
> >>
> >>Raghuraman R
> >>ASIC
> >>Texas Instruments (India) Ltd.
> >>Phone : +91-80-5099113
> >>http://www.india.ti.com/~raghu
> >>
> >>* Think. *
> >
> >
> >
>
>
>--
>Regds,
>
>Raghuraman R
>ASIC
>Texas Instruments (India) Ltd.
>Phone : +91-80-5099113
>http://www.india.ti.com/~raghu
>
>* Think. *



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