Subject: Re: [sv-bc] Summary of voting for all committees
From: Simon Davidmann (simon@his-home.demon.co.uk)
Date: Fri Apr 25 2003 - 11:46:19 PDT
At 06:39 PM 4/25/2003, David W. Smith wrote:
>Greetings,
>
>In the committee chair's meeting this morning I was asked to create a
>summary of all of the votes in each of the committees. The attached file
>contains the summary that will be placed on the web site.
>
>I organized it into a single table in order to save room.
>
>Thank you one and all. This is an impressive accomplishment.
I think getting all the votes lined up is a real impressive accomplishment
- and yes a lot of work has been completed to get to where we are today.
However - I do have the concern that several people, including a major
force in the industry - Cadence - has clearly shown that there are
significant problems with the current snapshot status in the evolution of
Verilog - and I believe we need to take the time to address these
significant concerns - otherwise we could face the situation where not only
will we have multiple languages to support - e.g. Verilog, VHDL, SystemC,
Vera, e, ... etc but the major one - Verilog will have different
incompatible dialects - which will destroy the concept of standard
languages - and not only will we have wasted a lot of committee efforts in
getting consensus we will be back to the problems we had in the mid
70's/early 80's where every vendor had their own language.
If we ignore current language design problems and rush to standardize an
unfinished language I believe we will be moving to an era of proprietary
incompatible language flavors which will slow EDA evolution dramatically.
The people who would suffer most from this backward step would be the EDA
vendors.
Simon.
>
>Regards
>David
>
>
>David W. Smith
>Synopsys Scientist
>
>Synopsys, Inc.
>Synopsys Technology Park
>2025 NW Cornelius Pass Road
>Hillsboro, OR 97124
>
>Voice: 503.547.6467
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>Email: <mailto:david.smith@synopsys.com>david.smith@synopsys.com
>http://www.synopsys.com
>
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