Subject: RE: [sv-cc] Re: [sv-bc] Summary of voting for all committees
From: Simon Davidmann (simon@his-home.demon.co.uk)
Date: Fri Apr 25 2003 - 15:06:18 PDT
Joao,
Nope I am not making the assumption that only Cadence has good language
designers, I don't recall saying they did or did not have any - and in fact
- I don't think many companies do - and in fact there are only about 3-4
good language designers in EDA - people with the cleanliness of thought to
really get things right.
And the more people you get significant involvement from - the worse the
situation potentially becomes.
And the more issues you listen to and arrive at solutions for - the worse
it becomes.
The only language that I can recall that has had about as much efforts as
3.1 is Esperanto - and as I am sure you are aware - several countries
decided that actually it did not have the right features for them.
Having been involved with a couple of language design efforts I know that
you need to keep polishing them until they work properly and are clean -
most amateur language designers just don't get it. For example - in
SystemVerilog we want to be able to wait for events, and now we have the
requirement that we want to wait for them in sequence - so why are there 3
different incompatible ways to do it in 3.1? Another example - why can I
only randomize things in classes? Why can I not instance modules in
interfaces, etc etc. - what you need is to polish, and then polish more and
then polish it more - and when it is is clean - then you can stop
polishing. And to polish you need to see and understand the whole language.
When in doubt - have a look at how simple C is - and how cleanly it works -
and how sweet the original K&R is as an example of a language manual - and
how it draws you in - and how the language is small and how unbelievably
powerful.
For every item you put in - you should take out two... or at least simplify
them...
One construct in SUPERLOG took us almost 5 years of polishing to get right.
Hey - don't get me wrong - I think the concept of SystemVerilog - a unified
HDVL is right on - no question. An unbelievably powerful concept.
I just don't think that because you get majority agreement in a committee
on certain constructs that they are good, or even good enough, or in fact
any good at all - just because we all think the world is flat - does not
make it flat - its just we have not spent enough time exploring it. And
actually believing the world to be flat is OK when you are just concerned
with say sailing around in the Mediterranean sea. There are only 3-4 people
that can see things clearly enough to get things really right - most of us
make wrong assumptions - and this is the problem - we just don't know better.
I agree that a lot of people have put a tremendous amount of effort in 3.1
and it is not for me to pass any judgement on it - but if several of the
committee members have serious doubts - then it seems to me that these
issues need resolving, not out-voting. After all - as an industry we do
need one consensus language and as Mulder and Scully state - 'the truth is
out there'.
If you want to continue this discussion - buy me a beer at DAC.
Simon
At 08:12 PM 4/25/2003, Joao Geada wrote:
>Simon,
>
>You are making the assumption that only Cadence has good language
>designers and that only they are qualified
>to find issues and comment on this standard. I beg to differ: there was
>significant involvement in this standard from
>a wide field of contributors, including from the user community, IEEE and
>major EDA vendors and including Cadence.
>We have all spend a significant amount of time, effort and talent working
>on the issues and making diligent effort to reach
>working, realistic solutions to the issues that were identified as we went
>along. All issues raised were listened to and we
>arrived at solutions that we acceptable to the majority of contributors
>(clearly, as in all cases the majority has voted to accept).
>
>As with any committee based entity, not all compromises will please all
>people all the time, and sure, in some cases there
>are alternate solutions possible. I do not believe we claim that this is
>the *only* possible way to do Verilog extensions; however,
>it is a *valid* way to do so, and the proof has been that the result has
>been found acceptable to the large majority of contributors.
>
>Joao
>
>==============================================================================
>Joao Geada, PhD Principal Engineer Verif Tech Group
>Synopsys, Inc TEL: (508) 263-8083
>377 Simarano Drive, Suite 300, FAX: (508) 263-8069
>Marlboro, MA 01752, USA
>==============================================================================
>
>-----Original Message-----
>From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org]On Behalf Of Simon
>Davidmann
>Sent: Friday, April 25, 2003 2:46 PM
>To: sv-ac@eda.org; sv-bc@eda.org; 'sv-cc'; sv-ec@eda.org
>Subject: [sv-cc] Re: [sv-bc] Summary of voting for all committees
>
>At 06:39 PM 4/25/2003, David W. Smith wrote:
>>Greetings,
>>
>>In the committee chair's meeting this morning I was asked to create a
>>summary of all of the votes in each of the committees. The attached file
>>contains the summary that will be placed on the web site.
>>
>>I organized it into a single table in order to save room.
>>
>>Thank you one and all. This is an impressive accomplishment.
>I think getting all the votes lined up is a real impressive accomplishment
>- and yes a lot of work has been completed to get to where we are today.
>
>However - I do have the concern that several people, including a major
>force in the industry - Cadence - has clearly shown that there are
>significant problems with the current snapshot status in the evolution of
>Verilog - and I believe we need to take the time to address these
>significant concerns - otherwise we could face the situation where not
>only will we have multiple languages to support - e.g. Verilog, VHDL,
>SystemC, Vera, e, ... etc but the major one - Verilog will have different
>incompatible dialects - which will destroy the concept of standard
>languages - and not only will we have wasted a lot of committee efforts in
>getting consensus we will be back to the problems we had in the mid
>70's/early 80's where every vendor had their own language.
>
>If we ignore current language design problems and rush to standardize an
>unfinished language I believe we will be moving to an era of proprietary
>incompatible language flavors which will slow EDA evolution dramatically.
>
>The people who would suffer most from this backward step would be the EDA
>vendors.
>
>Simon.
>
>
>
>
>
>
>
>>Regards
>>David
>>
>>David W. Smith
>>Synopsys Scientist
>>Synopsys, Inc.
>>Synopsys Technology Park
>>2025 NW Cornelius Pass Road
>>Hillsboro, OR 97124
>>
>>Voice: 503.547.6467
>>Main: 503.547.6000
>>FAX: 503.547.6906
>>Email: <mailto:david.smith@synopsys.com>david.smith@synopsys.com
>>http://www.synopsys.com
>>
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