Subject: Re: [sv-cc] Re: [sv-bc] Summary of voting for all committees
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Fri Apr 25 2003 - 16:18:18 PDT
Joao Geada wrote:
> Simon,
>
> You are making the assumption that only Cadence has good language
> designers and that only they are qualified to find issues and comment
> on this standard. I beg to differ: there was significant involvement
> in this standard from a wide field of contributors, including from the
> user community, IEEE and major EDA vendors and including Cadence. We
> have all spend a significant amount of time, effort and talent working
> on the issues and making diligent effort to reach working, realistic
> solutions to the issues that were identified as we went along. All
> issues raised were listened to and we arrived at solutions that were
> acceptable to the majority of contributors (clearly, as in all cases
> the majority has voted to accept).
I think the issue is that regardless of their quality there were too
many language designers involved - the original Verilog, C (via
Superlog), Java (via Vera) and Sugar etc. Too many cooks spoil the broth.
The whole is at best the sum of its parts (IMO).
> As with any committee based entity, not all compromises will please
> all people all the time, and sure, in some cases there are alternate
> solutions possible. I do not believe we claim that this is the *only*
> possible way to do Verilog extensions; however, it is a *valid* way to
> do so, and the proof has been that the result has been found
> acceptable to the large majority of contributors.
>
> Joao
All you have at the moment is an LRM, the final verdict won't be in
until people actually build some tools and simulators. I abstained on
the vote because I don't have to either use or build any SV tools,
Cadence on the other hand would have to invest significant amounts of
time and money building the tools and are entitled to their opinion that
the language is not in a fit state to make that investment.
Kev.
>
> ==============================================================================
> Joao Geada, PhD Principal Engineer Verif
> Tech Group
> Synopsys, Inc TEL: (508)
> 263-8083
> 377 Simarano Drive, Suite 300, FAX: (508)
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> Marlboro, MA 01752, USA
> ==============================================================================
>
> -----Original Message-----
> From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org]On Behalf Of
> Simon Davidmann
> Sent: Friday, April 25, 2003 2:46 PM
> To: sv-ac@eda.org; sv-bc@eda.org; 'sv-cc'; sv-ec@eda.org
> Subject: [sv-cc] Re: [sv-bc] Summary of voting for all committees
>
> At 06:39 PM 4/25/2003, David W. Smith wrote:
>
>> Greetings,
>>
>> In the committee chair's meeting this morning I was asked to
>> create a summary of all of the votes in each of the committees.
>> The attached file contains the summary that will be placed on the
>> web site.
>>
>> I organized it into a single table in order to save room.
>>
>> Thank you one and all. This is an impressive accomplishment.
>
>
> I think getting all the votes lined up is a real impressive
> accomplishment - and yes a lot of work has been completed to get
> to where we are today.
>
> However - I do have the concern that several people, including a
> major force in the industry - Cadence - has clearly shown that
> there are significant problems with the current snapshot status in
> the evolution of Verilog - and I believe we need to take the time
> to address these significant concerns - otherwise we could face
> the situation where not only will we have multiple languages to
> support - e.g. Verilog, VHDL, SystemC, Vera, e, ... etc but the
> major one - Verilog will have different incompatible dialects -
> which will destroy the concept of standard languages - and not
> only will we have wasted a lot of committee efforts in getting
> consensus we will be back to the problems we had in the mid
> 70's/early 80's where every vendor had their own language.
>
> If we ignore current language design problems and rush to
> standardize an unfinished language I believe we will be moving to
> an era of proprietary incompatible language flavors which will
> slow EDA evolution dramatically.
>
> The people who would suffer most from this backward step would be
> the EDA vendors.
>
> Simon.
>
>
>
>
>>
>> Regards
>> David
>>
>>
>> David W. Smith
>> Synopsys Scientist
>>
>> Synopsys, Inc.
>> Synopsys Technology Park
>> 2025 NW Cornelius Pass Road
>> Hillsboro, OR 97124
>>
>> Voice: 503.547.6467
>> Main: 503.547.6000
>> FAX: 503.547.6906
>> Email: david.smith@synopsys.com <mailto:david.smith@synopsys.com>
>> http://www.synopsys.com <http://www.synopsys.com/>
>>
>
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