Subject: Re: [sv-ec] Re: [sv-bc] Re: Post 3.1
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri May 09 2003 - 09:43:15 PDT
> From Jonathan.Bradford@Micronas.com Fri May 9 03:20:43 2003
>
> What about defining pragmas for backward compatability that apply over
> files / modules ?
> Then the syntax would be aware whether `bit', 'logic' etc were keywords
> or variables from 'older' code ?
>
> `verilog1995
> `verilog2000
>
> even for those stirring mixed signal flavours
>
> `verilogams
>
> These pragmas could also have meaning on the command line arguments
> for multi-pass compile/elaborate/sim invocations, but then they only
> apply to files,
> not individual modules and are of less help to the single pass sim
> invocations using -y
> scanning options etc.
>
> Just a simple suggestion.
>
> Jonathan Bradford
Given the other discussion on type equivalence it might be better to
do it slightly differently - just suppress the typedef for a while
rather than undefine it. An implementation of your suggestion could
be:
`define verilog1995 suppress bit,logic;
`define systemVerilog unsuppress bit,logic;
Then you could do -
`verilog1995 // ignore new types
`include "old_stuff.v"
`systemVerilog // reinstate new types
...
The definitions of `verilog1995 etc. can be predefined macros that
the user could undef and redefine if necessary.
NB: my original objective was to replace keywords with more flexible
constructs that cause fewer backward compatibility problems, so that
you don't have to switch parsers midstream.
Kev.
>
> Kevin Cameron x3251 wrote:
>
> > I previously posted suggesting that we could reduce the size of the
> > language and get better backward compatibility by reimplementing stuff
> > as typedefs in standard header files. It occured to me that you could
> > also do it by using pre-defined typedefs if you add an "untypedef"
> > capability. E.g. if you have bit & logic predefined (as per previous
> > discussion with Cliff) -
> >
> > typedef unresolved_bit bit;
> > typedef resolved_bit logic;
> >
> > - then you could do something like:
> >
> > untypedef bit;
> > untypedef logic;
> > `include "my_old_verilog.v" // old code using "bit" or "logic"
> >
> > You could consider "byte","short" & "int" as being:
> >
> > typedef signed unresolved_bit [7:0] byte;
> > typedef signed unresolved_bit [15:0] short;
> > typedef signed unresolved_bit [31:0] int;
> >
> > Just a thought,
> > Kev.
> > ----
> > National Semiconductor, Tel: (408) 721 3251
> > 2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090
>
> --
>
> ________________________________________________________________________________
>
> /\ Jonathan Bradford mailto:bradford@micronas.com
> \/
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