Subject: Re: [sv-bc] RE: [sv-ec] Question: logic & reg - what is the difference?
From: Kevin Cameron (sv-xx@grfx.com)
Date: Mon Jun 09 2003 - 21:41:20 PDT
> To: "Kevin Cameron" <sv-xx@grfx.com>
>
> Kevin Said:
> > >A "reg" is actually a composite object, it is the combination of a driver
> > >and a wire. When you write to it you are assigning to the driver and when
> > >you read you get the wire value (the resolution of all the drivers of the
> > >wire). "logic" is the (default) type of the driver.
>
> Steven Sharp said:
> > I am afraid you are confused here. A reg is not resolved. When you write
> > to it, you write to the actual value. When you read from it, you get the
> > last value that was written. It works just like a variable in a normal
> > programming language.
>
> I agree with Steve here. A reg is a variable in exactly the same sense
> as a variable in C. Drivers from reg objects are a consequence of their
> use, and *not* their existance. To wit:
>
> reg foo;
>
> wire bar = foo;
> wire bel = foo;
>
> Two drivers here, each associated with the continuous assignment. One
> might protest that even that is only one driver. In fact, a compiler
> may choose here to implement the two drivers as one driver with a fan-
> out of 2, but consider this:
>
> reg foo;
> reg bar;
>
> wire bat, bell;
> assign bat = foo;
> assign bat = bar;
> assign bell = foo;
>
> The compiler must make two drivers here, lest a single driver from
> reg foo would cause a connection between bat and bell, which is not
> correct.
In my book there are five drivers; the implicit drivers for foo and
bar are effectively optimised away if those signals are not connected
out of the module, each assign is a seperate process and creates it's
own driver for the target signal.
As I said in my first post my perspective is that of an AMS tool builder.
It's importand to know which objects are drivers so that you can convert
digital values to current/voltage correctly. Tool builders that only
deal with digital design don't care that much about these issues since
they are working in a higher level abstraction.
> So a reg is a variable, plain and simple. The drivers from a reg are
> aspects of assignments into nets, and I have the bug reports as proof:-)
> (In fact, a vpi_put_value to one of the nets bar or bel in the first
> example can further entangle you if you have the wrong model in your
> head.)
PLI aside, regs only behave like variables sometimes. Adding "logic" as
a type attempts to remove the confusion by letting you declare proper
variables rather than using the degenerate behavior of regs.
Kev.
This archive was generated by hypermail 2b28 : Mon Jun 09 2003 - 21:47:10 PDT