Subject: [sv-bc] RE: [sv-ec] Accellera SystemVerilog 3.1A Focus And Plans
From: Vassilios.Gerousis@Infineon.Com
Date: Fri Jun 13 2003 - 01:36:54 PDT
Hi Alec,
Thanks for the vote of confidence. There are many others who deserve
the credits of thanks.
Accellera Chairman will send you such a letter on behalf of
Accellera organization. On behalf of Accellera, we look forward to your
implementation of SystemVerilog and seek all feedback to us regarding issues
you discover in your implementation process. You should have no fear that
there are any issues that Accellera or technology donators would use against
you.
I would like to share with you that the donations to Accellera are made
such that any patents included in a donation would not be asserted by the
donor/patent holder in order to build a compliant application. The
Accellera technology donation policy on patents complies with IEEE's Patent
Policy subsection (a). This assures a smooth transition to the IEEE and
offers you the greatest flexibility since there are no patent concerns on
your part. And, it ensures there are no terms and conditions that would
allow "reasonable" license fees. There are no license fees for patents in
Accellera standards unless expressly allowed by the Accellera board. No
such rights have been granted to date.
Accellera will not work on any standard unless it goes through a
technology assignment letter. For each donations that ended up in
SystemVerilog we have done detailed examinations of all donors and their
patents. Since you are not a member of Accellera, you do not see the
analysis that we went through. In the case of SystemVerilog 3.0, we spent
almost two months in discussion with lawyers of Co-Design with respect to
the technology assignment letter to Accellera. We have done thorough
analysis prior to any examination of Superlog technology. I am pleased to
say that we have done more than an adequate job based on Accellera process
which is even stricter than IEEE patent process to satisfy ourselves. The
same analysis went into the Synopsys donations. We have gone through
rigorous analysis in regards to Synopsys donation. The Accellera technology
assignment letter signed by Synopsys allow everyone to implement
SystemVerilog with no licensing fees or any other concerns associated with
SystemVerilog related patents. We examine all donations based on business
aspects in accordance to Accellera policy and also technical aspect which
these committees went through several months of review cycle and ended up in
formal Accellera Acceptance to both Co-Design and Synopsys donations.
Both SystemVerilog 3.0 and 3.1 are available for anyone to implement
and use with no fees or no licensing or fear of patents from the original
donors or Accellera. However, this does not cover any other third patents
that may apply on such a technology. There are patents that are not from
original donors, that asserted some claims when we were in the development
of SystemVerilog 3.1. As an example, Michael McNamara has asserted the
existence of a Verisity patent on coverage. As a technical community we
examined such a patent and we do not see any issues in regards to
SystemVerilog Language. We pointed this to the committee and also to
Accellera Board which Verisity is a member. Neither Verisity or McNamara
have contested their claims against SystemVerilog standard or try to
cooperate with Accellera to provide a better transition to IEEE in this
area. The same applies to 0-in patent, which we analyzed and do not see
special claims to SystemVerilog. 0-in refused to cooperate in the same
manner as Verisity although their technical team continued their
participation after the claim was announced.
All of the above are public records that will be transferred to IEEE
when the appropriate time comes. Alec, this is not the first time that
Accellera has done this. This was done, during the development of OVI
Verilog, which I understand that Fintronics built a compliant OVI simulator
with no fear on patents. At that time, you did not request a public letter
to implement a Verilog simulator. We understand that time change and now
more attentions is being paid to patents and policy. I can assure you that I
personally will not work on a standard that has issues with patents or
conditions. The Accellera board is very clear about this policy and have
conducted serious examination by members such as Verisity and Cadence during
the donations process of 3.0 and 3.1. Accellera rules are very strict, that
Cadence lawyers have instructed their business units not to donate anything
to Accellera during SystemVerilog 3.1 donation period. Cadence wanted to
donate some datapath, assertion technology and other technologies. This is
documented in SV meeting minutes on May 2002. After three months donation
period, the Cadence business unit could not convince Cadence Lawyers. Also,
Accellera will not change its strict rules in this area.
Alec, you should pay more attentions to certain committees within
IEEE DASC working groups and demand the same conditions as Accellera provide
in terms of its published standards. As an example you should examine "E"
Language donation to IEEE working group and also Cadence donation to IEEE
1364. You should request that both committees obey IEEE's Patent Policy
subsection (a) and provide you with technology assignment letters to IEEE in
regards to technology donations and patents.
Looking forward to your SystemVerilog implementation and feedback.
Do not forget to become an Accellera member and help our process of making
3.1A a solid standard.
Best Regards
Vassilios
-----Original Message-----
From: Alec Stanculescu [mailto:alec@fintronic.com]
Sent: Thursday, June 12, 2003 6:41 PM
To: Gerousis Vassilios (CL DAT CS)
Cc: sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
Subject: Re: [sv-ec] Accellera SystemVerilog 3.1A Focus And Plans
Vassilios,
First, I want to congratulate you for your dedication to public standards
and for your success in your activities related to Verilog and System
Verilog. You truly made a difference. Second, I would like to congratulate
all the donors of technologies incorporated in System Verilog 3.1 which made
possible for System Verilog 3.1 to become a reality.
As I already stated to you privately, I believe that it would be nice if
Accellera would issue a public statement saying that:
1. It owns all rights to System Verilog 3.1.
2. There are no patents that would be inherently infringed upon by any
implementation of a simulator supporting System Verilog 3.1.
3. Accellera gives the right to any company to implement tools based on
System Verilog 3.1 and to sell such tools without any
dues/royalties/fee/etc. to be payed to Accellera or to any of the original
owners of the technologies donated to Accellera and incorporated in System
Verilog 3.1.
I understand from your private statements made to me that the content of
this letter is already implied by Accellera's public position, however an
official statement would help because:
i) a formal review of the donations to Accellera was not conducted by an
independent organization (such as the IEEE), nor by Accellera itself under
the pressure of a public statement, such as the proposed letter.
ii) being the owner of System Verilog, Accellera may make "half promises" in
good faith, which later it would not keep for reasons which make perfect
sense. By "half promises" I mean statements made by people involved with
Accellera's work, such as yourself, which do not fully legally bind
Accellera to make good on those promises.
iii) Usually donations are accompanied by conditions, and it is not clear
that all the conditions associated to each of the technologies donated to
Accellera and incorporated in System Verilog 3.1 are met, and therefore the
rights of Accellera over those donations may be questionable.
Wishing you continued success in your work,
Alec Stanculescu
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