Subject: [sv-bc] RE: [sv-ec] Accellera SystemVerilog 3.1A Focus And Plans
From: Jay Lawrence (lawrence@cadence.com)
Date: Fri Jun 13 2003 - 05:37:57 PDT
Vassilios,
Cadence has provided all required documentation on copyright, reprint
rights and patent assurance to the IEEE for our 1364 donations. Original
signed copies of these letters were provided to the appropriate IEEE
representatives, the DASC chair, and the 1364 working group chair. These
release letters are exactly the same letters provided with the original
donation of Verilog to OVI, the donation of the $random algorithms to
1364, and comply with all IEEE guidelines on donation submission with
respect to copyrights and patents.
There is no patented or patent pending material in the recent IEEE
donations made by Cadence.
Sincerely,
Jay Lawrence
> Alec, you should pay more attentions to certain
> committees within
> IEEE DASC working groups and demand the same conditions as
> Accellera provide
> in terms of its published standards. As an example you should
> examine "E"
> Language donation to IEEE working group and also Cadence
> donation to IEEE
> 1364. You should request that both committees obey IEEE's
> Patent Policy
> subsection (a) and provide you with technology assignment
> letters to IEEE in
> regards to technology donations and patents.
>
> Looking forward to your SystemVerilog implementation
> and feedback.
> Do not forget to become an Accellera member and help our
> process of making
> 3.1A a solid standard.
>
> Best Regards
>
> Vassilios
>
>
> -----Original Message-----
> From: Alec Stanculescu [mailto:alec@fintronic.com]
> Sent: Thursday, June 12, 2003 6:41 PM
> To: Gerousis Vassilios (CL DAT CS)
> Cc: sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
> Subject: Re: [sv-ec] Accellera SystemVerilog 3.1A Focus And Plans
>
>
> Vassilios,
>
> First, I want to congratulate you for your dedication to
> public standards
> and for your success in your activities related to Verilog and System
> Verilog. You truly made a difference. Second, I would like to
> congratulate
> all the donors of technologies incorporated in System Verilog
> 3.1 which made
> possible for System Verilog 3.1 to become a reality.
>
> As I already stated to you privately, I believe that it would
> be nice if
> Accellera would issue a public statement saying that:
>
> 1. It owns all rights to System Verilog 3.1.
>
> 2. There are no patents that would be inherently infringed upon by any
> implementation of a simulator supporting System Verilog 3.1.
>
> 3. Accellera gives the right to any company to implement
> tools based on
> System Verilog 3.1 and to sell such tools without any
> dues/royalties/fee/etc. to be payed to Accellera or to any of
> the original
> owners of the technologies donated to Accellera and
> incorporated in System
> Verilog 3.1.
>
> I understand from your private statements made to me that the
> content of
> this letter is already implied by Accellera's public
> position, however an
> official statement would help because:
>
> i) a formal review of the donations to Accellera was not
> conducted by an
> independent organization (such as the IEEE), nor by Accellera
> itself under
> the pressure of a public statement, such as the proposed letter.
> ii) being the owner of System Verilog, Accellera may make
> "half promises" in
> good faith, which later it would not keep for reasons which
> make perfect
> sense. By "half promises" I mean statements made by people
> involved with
> Accellera's work, such as yourself, which do not fully legally bind
> Accellera to make good on those promises.
> iii) Usually donations are accompanied by conditions, and it
> is not clear
> that all the conditions associated to each of the
> technologies donated to
> Accellera and incorporated in System Verilog 3.1 are met, and
> therefore the
> rights of Accellera over those donations may be questionable.
>
> Wishing you continued success in your work,
>
> Alec Stanculescu
>
>
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