Subject: [sv-bc] Time literal units suffixes
From: Stephen Williams (steve@icarus.com)
Date: Tue Jul 01 2003 - 14:09:52 PDT
The SystemVerilog LRM defines time literals to have the format
<digits> [ .<digits> ] (s|ms|us|ns|ps|fs|step)
So for example 1ns is a literal time. My question is whether the
units suffixes are keywords? It appears that they are *not* intended
to be keywords, but that can lead to some tricky parsing. To wit:
foo <= # 1 ns - 5;
If the ns is not a keyword, then the lexical analyzer could detect
that "1 ns" is a time literal and absorb it as a token. Then the -5
is the valid expression that gets assigned to foo.
If the "ns" is a keyword, then this becomes an error. That would be bad.
If time literals are not implemented, then this is the same as:
foo <= #(1) (ns - 5);
since "ns" is a valid identifier. In other words, one legal statement
before SV becomes a different legal statement after SV. That would
be *very* bad.
This may be resolved if the "ns" (or any other units suffix) shall
not have any white space between it and the number that it is
modifying. For example:
foo <= # 1ns - 5; // -5 after 1ns
foo <= # 1 ns - 5; // ns-5 after 1 local unit of time.
(Actually, as Verilog currently stands, the first above is valid
and is the same as #1 ns-5, because white space is not required
between the literal 1 and the identifier ns.)
This is awfully detailed, I realize, but I want to get it right,
and possibly get the LRM clarified. My vote is to require that
there be no white space between the digits and the suffix in a
time literal.
-- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
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