[sv-bc] Meaning of step in time literal

Subject: [sv-bc] Meaning of step in time literal
From: Stephen Williams (steve@icarus.com)
Date: Tue Jul 01 2003 - 14:14:32 PDT

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The time literal <value>step (for example 1step) is not defined
anywhere in the LRM, that I can see. I am going to guess that it
is meant to be a single tick of simulation precision, meaning
the greatest precision of all the modules in the simulation.

Thus, "1step" is guaranteed to be no larger then the smallest
delay anywhere else in the design. Is this correct? Can this
be clarified?

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

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