Subject: [sv-bc] User request for the SV-BC
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Wed Jul 16 2003 - 14:58:04 PDT
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>Date: Wed, 16 Jul 2003 15:28:55 -0500 (CDT)
>Message-Id: <200307162028.h6GKStE16293@farquaad.sps.mot.com>
>To: sv-bc@server.eda.org
>Subject: Multiple-concatenation/replication behavior
>From: Kurt Shultz <kurt.shultz@motorola.com>
>Reply-to: kurt.shultz@motorola.com
>
>
>All:
>
>I've recently been looking into the behavior of Synopsys VCS and
>Cadence Verilog-XL with regard to multiple concatenation when the
>replication count is zero. E.g., when the user writes:
>
> parameter FOO = <some_value>;
> wire [3:0] w;
> assign w = {1'b1,{(FOO-1){1'b1}},1'b1};
>
>the two simulators will assign w to 4'b0101 when FOO is 1 and to
>4'b0111 when FOO is 2. (VCS is kind enough to warn you about what it
>is doing when the replication count evaluates to zero.)
>
>In looking at the IEEE 1364-2001 LRM (section 4.1.14), a zero value
>for the replication count is explicitly forbidden.
>
>But the de facto standard, inferred from the two simulators, is that a
>replication operation evaluates to 1'b0 when its replication count
>evaluates to zero.
>
>I'm requesting that the SystemVerilog standard address this case
>explicitly as it is being used by some designers (perhaps knowingly,
>perhaps not) and the tools they are commonly using are accepting it.
>
>A search for "replication" in the SystemVerilog 3.1 LRM turned up
>table 3-2, which mentions only that the repetition count
>("multiplier") must be "of integral type". Section 7.11 doesn't
>describe any restriction on the multiplier, relying upon the
>definition from the Verilog standard.
>
>Related is the fact that, as far as I can tell, 1364 doesn't
>explicitly disallow negative replication counts, although that was
>probably intended.
>
>My apologies if this is not the right committee for this discussion.
>
>Cheers,
>Kurt
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