Subject: Re: [sv-bc] User request for the SV-BC
From: Steven Sharp (sharp@cadence.com)
Date: Wed Jul 16 2003 - 16:11:52 PDT
This should be referred to the IEEE 1364 ETF.
And since the ETF will probably change the requirement on the repeat count
from "non-zero" to "positive", making the nonpositive cases illegal, it is
not appropriate for SystemVerilog to try to define a particular behavior.
While the production of a 1-bit zero is the most common outcome in
Verilog-XL, with certain command line switches and with certain expressions
being replicated, Verilog-XL will produce other results. So this behavior
is not really defined even by the de facto standard.
Steven Sharp
sharp@cadence.com
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