Subject: Re: [sv-bc] User request for the SV-BC
From: Shalom.Bresticker@motorola.com
Date: Wed Jul 16 2003 - 23:46:32 PDT
The IEEE 1364 WG has already discussed this (issue #76) and passed the change
from "non-zero" to "positive" on March 10, 2003.
Shalom
On Wed, 16 Jul 2003, Steven Sharp wrote:
> Date: Wed, 16 Jul 2003 19:11:52 -0400 (EDT)
> From: Steven Sharp <sharp@cadence.com>
> To: sv-bc@eda.org, Karen.Pieper@synopsys.com
> Subject: Re: [sv-bc] User request for the SV-BC
>
> This should be referred to the IEEE 1364 ETF.
>
> And since the ETF will probably change the requirement on the repeat count
> from "non-zero" to "positive", making the nonpositive cases illegal, it is
> not appropriate for SystemVerilog to try to define a particular behavior.
>
> While the production of a 1-bit zero is the most common outcome in
> Verilog-XL, with certain command line switches and with certain expressions
> being replicated, Verilog-XL will produce other results. So this behavior
> is not really defined even by the de facto standard.
>
> Steven Sharp
> sharp@cadence.com
>
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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