Subject: RE: [sv-ec] RE: [sv-bc] Question on memory pattern file formats in SV
From: Chris Spear (Chris.Spear@synopsys.com)
Date: Thu Aug 21 2003 - 07:22:23 PDT
How would a sparse memory with only a few elements be written? The
simulator would need to write a set of address / data pairs.
Even non-sparse memories can be non-trivial to dump using file I/O.
The lower and upper bounds have to be coded into the loops.
Support for multi-dimensional arrays in $readmem is not too hard.
The task call would need to allow multiple indices for the starting
address. Likewise, the file format would have to allow address
with multiple indices, such as @1, 3, 4 for mem[1, 3, 4]
We will need to define what happens when the end of a "row" is
reached, and which dimension varies the fastest.
I tried to write this in Vera but the lack of parameterized types
made it too narrow.
Chris Spear
-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org]On Behalf Of
Warmke, Doug
Sent: Wednesday, August 20, 2003 8:53 PM
To: 'Steven Sharp'; sv-ec@eda.org; sv-bc@eda.org
Subject: [sv-ec] RE: [sv-bc] Question on memory pattern file formats in
SV
Steve,
Thanks for the quick answer.
A couple of things to consider:
1) Performance will be better with all memory file I/O
handled by $readmem and $writemem.
2) In case a simulator implements a sparse
memory concept, user-created for loops
may be quite difficult to implement correctly.
Smart $readmem/$writemem could handle the
sparse architecture, however.
Regards,
Doug
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