[sv-bc] RE: SystemVerilog Requirements Gathering Meeting

[This may be a repeat to a message you have already seen. I have been
told the reflectors rejected the email. Please ignore if you already
got this message and have responded. I will submit final counts on
Tuesday, 23 February 2010 at 3pm PST.]

All,

  For all those who have ACCPETED the meeting invitation, I will assume
you will participate in person. (Count need for catering.) For those
who have indicated TENTATIVE meeting acceptance, I will assume you might
join via WebEx/Teleconference and not in person. If you have better
clarity of your travel plans today and will be present, please let me
know.

  I will also presume those who are presenting will do so in person and
add you to the count for seating space allocation and catering. If this
is not the case, just let me know and I will list you as a
WebEx/Teleconference participant.

  TELECONFERENCE ATTENDEES: Please note, due to the number of in-person
participants, we will be in a larger room that is not be conducive for
high-quality teleconference connections. Your ability to hear all the
conversations will be greatly impaired. Active teleconference
management will be in play where muting of all lines may be enforced
during presentations to prevent other callers from cutting out the
presentation being given.

  If you need to update your attendance, please reply to the following.
Later today, I will send email confirmations to those I have listed to
attend.

_____ I will attend in person.
                DIETARY RESTRICTIONS (leave blank for none)
________________________________________________

_____ I will attend via WebEx/Teleconference

Regards,

Dennis

-----Original Appointment-----
From: Brophy, Dennis
Sent: None
To: B1.108 Valiant; 'IEEE P1800 Working Group'; 'sv-ac@eda.org';
'sv-bc@eda.org'; 'sv-cc@eda.org'; 'sv-ec@eda.org'; 'stds-dasc@eda.org'
Cc: 'Anand Gurusamy'; 'Yatin Trivedi'; 'Zhen Liu'; 'Tsuneyoshi Yakabe';
Rich, Dave; 'Mirmak, Michael'; 'Bassam Tabbara'; 'Geishauser
Joachim-R38313'; 'ssmith@synopsys.com'; 'Lavva, Irina'; 'David
Long/doulos'; 'Even-haim, Daniel'; 'Bresticker, Shalom'; 'Surrendra
Dudani'; 'Delp, Gary'; 'Scott Cranston'; 'Rivette Zack-RZZZ40';
'thanapoom.lertpanyavit@intel.com'; 'Bullis, Bryan'; 'Chuck Berking';
'Premduth Vidyanandan'; 'Rozenberg Idan-B08218'; 'Dave Cronauer';
Bailey, Stephen; 'Dongxiang Wu'; 'Brad Pierce'; 'Eduard Cerny'; 'Arif
Samad'; 'Karen Bartleson'; Gran, Alex; 'Hirschi Ross-QRH000'; 'Jim
Robinson'; 'Mark Hartoog'; 'Miller Hillel-R53776'; Larsen, Kenneth;
'Arturo Salz'; 'hmcdvi@msn.com'; Ryan, Ray; Abraham.Si@maxim-ic.com;
Shields, John
Subject: SystemVerilog Requirements Gathering Meeting
When: Friday, February 26, 2010 8:00 AM-5:00 PM (GMT-08:00) Pacific Time
(US & Canada).
Where: Mentor Graphics, 1001 Ridder Park Dr, San Jose, CA 95131 or
Teleconference

**** SAVE THE DATE ****

The IEEE P1800 SystemVerilog Working Group will hold an open meeting the
day after the DVCon conference on February 26th to gather input on what
should be included in the next revision of the SystemVerilog standard.
Your participation is encouraged and welcomed. You are also encourage
to share this invitation with others you believe have an interest to
provide input into the next revision of the standard.

The IEEE SystemVerilog Working Group recently finished its work with the
completion of the IEEE Std 1800-2009(tm) standard. The group is looking
to renew its authorization to work on an update (revision) to that
standard. The revision can address errata and use issues along with
extensions and changes to improve adoption and expanded use as suggested
by meeting participants. The information gathered at this meeting will
be used to establish the scope of the next revision project to initiate
standardization work. If you have input as to what should be addressed
in the next standard, you should participate in this meeting.

The meeting will be a face-to-face meeting to facilitate interactions
between attendees. Teleconference and WebEx facilities will also be
provided for those who may not be able to attend the face-to-face
meeting and also wish to participate.

If you wish to attend, please RSVP to Dennis Brophy (dennisb@model.com
<mailto:dennisb@model.com?subject=IEEE%20SystemVerilog%20Meeting%20Atten
dance%20RSVP> ) or accept this meeting request if your email tool
supports .iCalendar.
      (Your will later be asked about any dietary considerations.)
If you wish to present at the meeting, please RSVP to Karen Pieper
(karen_l_pieper@yahoo.com
<mailto:karen_l_pieper@yahoo.com?subject=IEEE%20SystemVerilog%20Presenta
tion%20Request%20RSVP> ).

DATE: 26 February 2010
TIME: 8:00 a.m. - 4:00 p.m. PST (Breakfast & Lunch provided)
LOCATION: Mentor Graphics Corporation
                       Valiant Conference Room (B1-108)
                       1001 Ridder Park Drive
                       San Jose, CA USA 95131
                       Directions
<http://www.mentor.com/company/office_locations/headquarters/directions_
sv> to meeting
TELECONFERENCE INFORMATION:
                       Toll-Free: 800-637-5822 (US & Canada)
                       Caller Paid/International: +1 647-723-3937
                       Toll-Free Numbers
<https://g8.cfer.com/g8.jsp?an=8006375822&ac=6850893&login=true>
Outside the United States or Canada
                       Access Number: 6850893

AGENDA: To be furnished later.

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You scheduled this meeting.

Meeting Number: 752 295 744
Meeting Password: ieee1800

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