RE: [sv-bc] expressions not allowed in RHS or continous assign or on port connection list

Shalom,

This particular case was not just about writing bad code, but writing
bad code that performs equally badly across all implementations. People
really, really want interoperability. They do not want features whose
results are "implementation dependant". Sometimes, language restrictions
are there for future removal until their results can be made
deterministic. That may or may not ever happen.

If we don't put in this particular restriction, then users start writing
code dependant on implementation A. Other users start writing code
dependant on a different implementation B, which might be incompatible
implementation A. Then we're stuck trying to put this into the LRM.

Dave

> -----Original Message-----
> From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
> Sent: Wednesday, April 07, 2010 8:05 PM
> To: Steven Sharp; john@svtii.com; sv-bc@eda.org; Rich, Dave
> Subject: RE: [sv-bc] expressions not allowed in RHS or continous
assign
> or on port connection list
>
> There has been in recent years a tendency to try to make illegal
various
> construct uses on the grounds that the user *might* write something
that
> causes problems instead of "trusting the user to write a reasonable
> function" and warning him to avoid certain uses that would cause
> problems, thereby outlawing certain useful forms.
>
> SV and Verilog have come under criticism both for being too lenient
(by
> those who like strict type-checking, etc.) and for being too strict.
Both
> camps often bring VHDL as a counter-example. I personally favor the
> lenient school, relying on coding guidelines to guide users and on
code
> checkers to detect bad uses.
>
> Shalom
>
>
> > Yes, it is possible for a user to call a function in a
> > continuous assignment
> > which has a side effect. This could cause a problem.
> > However, it is also
> > possible that the user has correctly written a pure function
> > that does not
> > have any side effects. Rather than specifying extra rules
> > about what kind
> > of functions are legal here, the LRM may be trusting the user
> > to write a
> > reasonable function. And function calls are too useful to be
outlawed
> > completely here. Making certain functions illegal here would
> > also not be
> > backward compatible with Verilog.
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