Re: [sv-bc] expressions not allowed in RHS or continous assign or on port connection list

Hi.

Minor point of terminology:

I agree that the ++ operation in the argument list
of a nonprocedural function call should not be allowed.
However, I would not call it a "side effect".

The increment is unrelated to the function; it is applied
directly to the variable being used as a real parameter
in the call. This is what makes it illegal. If it were
in the function body, or perhaps applied to a formal
parameter of the function, an increment of a variable declared
outside the function would be causing what I would
call a side effect.

On 04/07/2010 04:56 PM, Steven Sharp wrote:
> Yes, it is possible for a user to call a function in a continuous assignment
> which has a side effect. This could cause a problem. However, it is also
> possible that the user has correctly written a pure function that does not
> have any side effects. Rather than specifying extra rules about what kind
> of functions are legal here, the LRM may be trusting the user to write a
> reasonable function. And function calls are too useful to be outlawed
> completely here. Making certain functions illegal here would also not be
> backward compatible with Verilog.
>
> On the other hand, an assignment operator or increment/decrement is certain
> to have a side effect. It is not unreasonable to outlaw it. It also is
> not incompatible with Verilog, since Verilog did not have these operators.
>
> An output or inout argument on a function is also going to have a side
> effect (aside from the corner case where the inout always assigns back the
> same value passed in, making the argument useless). So again, it is not
> unreasonable to outlaw it. And again, this is not incompatible with Verilog,
> since Verilog function arguments could not be output or inout.
>
> So you can regard this as outlawing cases that obviously have side effects,
> while continuing to allow cases that might or might not have side effects,
> and without making the rules too complex.
>
> Or you can regard this as eliminating side effects here as much as possible,
> without creating a backward incompatibility with Verilog.
>
> Steven Sharp
> sharp@cadence.com
>
>

-- 
      John Michael Williams
      Senior Adjunct Faculty
Silicon Valley Technical Institute
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