Re: [sv-bc] expressions not allowed in RHS or continous assign or on port connection list

Thanks, Steve, you beat me to the general explanation.

Let me add a specific example to this (one that most users
don't realize is problematic).

Assume you have:

    wire [3:0] w;
    assign w = a + b + c++;
    bit a = 0;
    bit b = 0;
    int c = 0;

and have:

    intial begin
       a = 1;
       b = 1;
       $display("%d", w);
    end

The output of "w" is in fact ambiguous. The LRM says
nothing about *when* the continuous assignment is
evaluated relative to the two sequential assignments
to "a" and "b".

So it would be valid to get a displays of numerous
values for w. The simulator initialization comes
into play as well as whether the continuous assign happens
after each of the a/b updates, after both, or not until the
initial process finished. There are no rules in the LRM
stating what *must* happen other than the basic fact that the
assignment will update the RHS expression value (before the
active region is empty). But exactly when/how the simulator
does that is undefined.

Gord.

Steven Sharp wrote:
>> Date: Fri, 09 Apr 2010 11:37:41 -0700
>> From: John Michael Williams <john@svtii.com>
>
>> I think what you mean is that there is no guarantee of the
>> sequence of execution of a continuous assignment relative
>> to other concurrent blocks (such as always or initial).
>
> This is not just an issue of ordering relative to other
> concurrent blocks in time slices when a continuous assignment
> evaluates. Whether a continuous assignment will evaluate at
> all in a given time slice is not well-defined. If there is
> a change in one of its operands that would change the value
> of the expression, then it must evaluate. But it might or
> might not evaluate in some other situations. If it evaluates
> extra times but keeps getting the same result, this doesn't
> matter as long as there are no side effects of the evaluation.
>
> For example, consider the assignment
>
> assign out = vector[3];
>
> Should this be evaluated only when bit 3 of vector changes?
> Or can it evaluate whenever vector changes, with the selection
> of bit 3 being part of the evaluation? The LRM doesn't really
> specify this, nor should it. Implementations need to be free to
> do this however they choose. In practice, this may depend on
> whether vector is a variable or a net, and whether the net is
> vectored or scalared. And as long as there are no side effects,
> the difference is invisible.
>
> Any side effect that exposes exactly when or how often a
> continuous assignment expression is evaluated is not going to
> behave in a predictable or portable way.
>
>
> Steven Sharp
> sharp@cadence.com
>
>

-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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