Re: [sv-bc] expressions not allowed in RHS or continous assign or on port connection list

>Date: Fri, 09 Apr 2010 14:55:17 -0700
>From: Gordon Vreugdenhil <gordonv@model.com>

Or a slight variation on your example:

Assume you have:

    wire [3:0] w;
    assign w = a + b + c++;
    bit a = 0;
    bit b = 0;
    int c = 0;

and have:

    initial begin
       a = 1;
       a = 0;
       $display("%d", w);
    end

>So it would be valid to get a displays of numerous
>values for w. The simulator initialization comes
>into play as well as whether the continuous assign happens
>after each of the a/b updates, after both, or not until the
>initial process finished.

This variation adds another possibility: the simulator waits
until after both updates, and then doesn't evaluate the
continuous assignment at all, since 'a' went back to its
original value.

Another issue is whether the change in the value of c during
the evaluation of the continuous assignment would cause another
evaluation of the continuous assignment, since c is an operand
of the assignment and it changed value. This would put the
simulation into an infinite zero-delay loop. With a similar
combinational always block, we know that an update within the
block would not "trigger" the always block, since the always
block is not waiting at an event control if it is currently
executing a blocking assignment. But a continuous assignment
is a "black box" whose internal workings are not specified to
this level of detail. So I don't think you can rule out the
possibility of self-triggering for it based on the LRM text.

Steven Sharp
sharp@cadence.com

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