[sv-bc] Top 25 issues

I would like to add Mantis 3048 to list of candidates for top 25. This issue may be consolidated with Gord's issue 3047.

Text for 3048:

Section 33.4 Configurations says "A configuration may change the binding of a module, primitive, interface, or program instance, but shall not change the binding of a package."

Configurations can change the binding of an interface instance, but it is unclear how interface ports and virtual interface variables are bound.

Generally, in System Verilog type identifiers are bound at parsing time. Modules are bound at elaboration time and that binding can be controlled by configurations. Virtual interface variables are described as types. It is not clear that this means the interface declaration must be seen before you can parse a virtual interface variable for it. Interface ports are not really types (you cannot for example pass an interface port type with a type parameter). It is also unclear whether interfaces declaration must be seen before it can be used as an interface port.

The LRM is not clear how interface names in virtual interface variables and interface port declarations are bound to interfaces.

This is an issue that users are already facing. If separate libraries are developed by different groups and they both have interfaces of the same name in them it can be very difficult to use these two libraries together.

0003047<http://www.eda.org/svdb/view.php?id=3047> also mentions this issue for virtual interfaces, but it exists for interface ports also.

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