Hi David.
I always use leading commas. This seems to be an adequate solution.
I don't like yet-another-diversity-enhancement to allow semicolons;
the first semicolon should end the header.
However, making optional a trailing port or parameter name in the list
might be useful. This would be identical to making a trailing comma
legal. I think making a trailing comma legal in ANY list might not
be harmful.
I sympathize with the cut-and-paste (or compiler macro) problem:
One of the most aggravating properties of Pascal was that the last
statement in a block HAD to end with whitespace; an optional
semicolon, used in every other line in the block, was forbidden.
By contrast, C used a semicolon on every line -- consistency
definitely is better than diversity, when writing code.
On 04/26/2010 01:38 PM, Gates, David wrote:
> Hi,
>
> I'd like to add a proposal that is somewhat related to Item n/a 10:
>
> (10) ANSI style ports and parameters - allow either comma or semicolon separators (slide 36)
>
> It can either be a separate item to vote on, or combined with n/a 10.
>
> When generating or transforming Verilog code, it is common to iterate over a list of items such as port declarations or connections. Currently in such cases, the generation code must take into account whether an item is the first or last when deciding whether to insert a comma between items. This is annoying all on its own, but is especially problematic when generating code that may be conditionally parsed:
>
> module foo (
> `ifdef NEED_PORT_A
> input a,
> `endif
> `ifdef NEED_PORT_B
> input b
> `endif
> );
> endmodule
>
> module bar();
> foo foo (
> `ifdef NEED_PORT_A
> .a(a),
> `endif
> `ifdef NEED_PORT_B
> .b(b)
> `endif
> );
> endmodule
>
> If NEED_PORT_A is defined but NEED_PORT_B isn't, then you get syntax errors. You can try to use leading commas instead:
>
> module foo (
> `ifdef NEED_PORT_A
> input a
> `endif
> `ifdef NEED_PORT_B
> , input b
> `endif
> );
> endmodule
>
> module bar();
> foo foo (
> `ifdef NEED_PORT_A
> .a(a)
> `endif
> `ifdef NEED_PORT_B
> , .b(b)
> `endif
> );
> endmodule
>
> But now if NEED_PORT_A is undefined and NEED_PORT_B is defined, you get different syntax errors. It's actually quite difficult to write legal code for all 4 cases (especially given the absence of a `if or `ifeq in the preprocessor.) Add more ports and things get exponentially worse.
>
> However, if you allow trailing commas, then it's possibly to generate "safe" code in all cases, and also it's no longer necessary to detect the first or last item as a special case.
>
> So the proposal is to allow trailing commas at the end of named connection lists and ANSI-Style port declaration lists:
>
> list_of_port_connections ::=
> ordered_port_connection { , ordered_port_connection }
> | named_port_connection { , named_port_connection } { , }
>
> list_of_port_declarations ::=
> ( [ { attribute_instance} ansi_port_declaration { , { attribute_instance} ansi_port_declaration } { , } ] )
>
> This becomes somewhat more important if you also consider Mantis 210, that would extend generate functionality to these same lists. In that case, you have to decide what form of separator / terminator is needed for the generated ports / connections.
>
> An alternative to the proposed enhancement would continue to restrict use of comma as a port / connection item _separator_ and add the option of using semicolon as a port / connection item _terminator_.
>
> ~ Dave
>
> // David A. Gates, Ph.D. 408.749.4497
> // Director, RTL Center of Expertise
> // Fellow, Design Automation
> // Advanced Micro Devices www.amd.com<http://www.amd.com/>
> // Less talk, more action.
>
>
-- John Michael Williams Senior Adjunct Faculty Silicon Valley Technical Institute -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Apr 26 14:22:09 2010
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