[sv-bc] Are variable-width part selects already part of the SV language? (Mantis 2684)

- 1 --- In http://www.eda.org/svdb/view.php?id=2684 , Shalom requests --------------------

Non-constant width part selects

- 2 --- In http://www.eda.org/svdb/view.php?id=2684#c9352 , Dave writes ------------------

I believe this can be handled in the context of a bitstream cast or streaming operator. In the same manner that we allow casing from dynamic to fixed sized unpacked arrays, we could apply the same rules to dynamically sized part selects. As long as the fixed or dynamic size target can accommodate the fixed or dynamically sized source, it should be legal. 

So the only change required is to allow variable sized part selects as a component of a bitstream cast or streaming operator.

- 3 --- In http://www.eda.org/svdb/view.php?id=2684#c9376 , I write ----------------------

I like Dave's suggestion, but don't we already have the capability he describes, as long we lift the arbitrary restriction that the left operand in a stream_expression must be unpacked?

 lhs = { << { v with [i:j] }};

A gotcha would be that if there are not enough bits to fill the left-hand side variable, then the 0-padding is on the right.

To use { << { v with [i:j] }} directly in an arithmetic expression, one would need to cast it to some type, as mentioned in http://www.eda.org/svdb/view.php?id=1401 .

So if this is legal

module test(input int i, j, input logic v_in[0:1000], output [0:15] v_out);
  assign v_out = {<< {v_in with [i:j]}};
endmodule

why not also the following?

module test(input int i, j, input logic [0:1000] v_in, output [0:15] v_out);
  assign v_out = {<< {v_in with [i:j]}};
endmodule

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-- Brad

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