RE: [sv-bc] Section 28.9 typo

Verilog-XL has a compiler directive to remove gate names in order to reduce memory consumption.

Shalom

> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com]
> Sent: Friday, May 07, 2010 7:29 AM
> To: Bresticker, Shalom; Greg.Jaxon@synopsys.com
> Cc: sv-bc@eda.org
> Subject: Re: [sv-bc] Section 28.9 typo
>
> The reason this is only allowed for primitives is that modules need
> to have a hierarchical name to get to anything inside. Primitives
> don't have anything accessible inside. I have seen netlisters use
> this syntax, avoiding the need to create instance names for the
> primitives, and shrinking the netlist.
>
> Since UDPs are primitives, and you can't tell whether an instantiation
> is a UDP or a module until elaboration, this means that
> missing instance
> names on module instantiations can't be caught until elaboration.
>
>
> Steven Sharp | Architect | Cadence
>
> P: 508.459.1436 M: 774.535.4149 www.cadence.com
>
>
>
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