RE: [sv-bc] RE: [sv-ec] Are variable-width part selects already part of the SV language? (Mantis 2684)

Yes, I looked at this.

That may be one of the reasons that VHDL simulation was stated in the past to be slower than Verilog. I don't know whether that is still true.

I also looked at what VHDL part-selects are considered synthesizable. The main differences are that (1) variables that are assigned constant values are allowed, and (2) loop index variables (called "parameters" in VHDL) are allowed. Loop unrolling allows the synthesis tool to treat them as constants.

Regards,
Shalom

> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On
> Behalf Of Paul Graham
> Sent: Friday, May 07, 2010 4:44 PM
> To: Bresticker, Shalom
> Cc: sv-bc@eda.org; SV_EC List; brad pierce; Dave Rich
> Subject: Re: [sv-bc] RE: [sv-ec] Are variable-width part
> selects already part of the SV language? (Mantis 2684)
>
> For what it's worth, variable width and variable offset part
> selects have always been part of vhdl. Vhdl has no special
> syntax to distinguish variable part selects from constant
> part selects, so a tool has to do some analysis to see which
> forms it can support and which it can't.
>
> Paul
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.