RE: [sv-bc] RE: [sv-ec] Are variable-width part selects already part of the SV language? (Mantis 2684)

I believe this would cover a large percent of the cases.

Shalom

> -----Original Message-----
> From: bradpiercephd@gmail.com
> [mailto:bradpiercephd@gmail.com] On Behalf Of Brad Pierce
> Sent: Friday, May 07, 2010 6:34 PM
> To: Bresticker, Shalom
> Cc: Rich, Dave; sv-bc@eda.org; SV_EC List
> Subject: Re: [sv-bc] RE: [sv-ec] Are variable-width part
> selects already part of the SV language? (Mantis 2684)
>
> So it would be sufficient to allow them to be operands in a
> concatenation in an assignment-like context?
>
> -- Brad
>
> On Fri, May 7, 2010 at 5:39 AM, Bresticker, Shalom
> <shalom.bresticker@intel.com> wrote:
> > A recent example was something like this:
> >
> > We have a 128-bit input vector and a 128-bit replacement
> vector. N indicates the replacement point. That is, the
> output vector needs to be composed of bits [127:N] from the
> input vector and bits [N-1:0] of the replacement vector.
> >
> > The actual case was more complex, and I am not sure I am
> summarizing it correctly.
> >
> > So, the intutitive but illegal way to code this is
> >
> > out[127:0] = { in[127:N], replace[N-1:0] } ;
> >
> > To actually get this, you can do something like (I'm not
> sure this is correct):
> >
> > {(in >> N), replace << (127-N)} >> N
> >
> > There are other ways to do this.
> > All are ugly, non-intuitive, hard to read, and even harder
> to write correctly.
> > The fact that there are ways to do this means that there
> are ways to transform the currently illegal form into a legal form.
> > Why shouldn't this transformation be automatic instead of
> forcing the designer to waste his time doing code contortions
> and usually requiring several passes until he gets it correct?
> >
> >> Often, what is needed is a combination of variable
> >> part-selects that adds up to a constant width, e.g., N bits
> >> from vector A, concatenated with 32-N bits from vector B.
> >
> > Shalom
> >
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