Re: [sv-bc] RE: [sv-ec] Are variable-width part selects already part of the SV language? (Mantis 2684)

From: Greg Jaxon <Greg.Jaxon@synopsys.com>
Date: Fri May 07 2010 - 22:22:51 PDT

Shalom's example illustrates how flawed the Verilog part select notation is when used algebraically.
Examine carefully the result for his and your expressions when N=0 (i.e. the input is not to be replaced).

Brad Pierce wrote:

Steven,

A simple change would be to lift the restriction that the left operand
in a stream_expression must be unpacked, as suggested in bullet 3 of

  http://www.eda.org/sv-bc/hm/10176.html

so Shalom's example could be written as

  out[127:0] = { << { in with [127:N]}, replace with [N-1:0] }} ;

which is already legal today when 'in' and 'replace' are unpacked.

-- Brad

On Fri, May 7, 2010 at 5:58 PM, Steven Sharp <sharp@cadence.com> wrote:
  

I'm not converging either.  I would like to understand the intended uses
better first.  I am leary of using variables in part-selects with a bunch
of special-case restrictions.  I would prefer to see if we can design a
a construct that inherently avoids the problems that are avoided by those
restrictions.


Steven Sharp   |   Architect   |   Cadence

P: 508.459.1436   M: 774.535.4149   www.cadence.com



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This message has been scanned for viruses and
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believed to be clean. Received on Fri May 7 22:23:35 2010